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X9C102, X9C103, X9C104, X9C503
Data Sheet December 20, 2006 FN8222.1
Digitally Controlled Potentiometer (XDCPTM)
FEATURES * Solid-state potentiometer * 3-wire serial interface * 100 wiper tap points --Wiper position stored in nonvolatile memory and recalled on power-up * 99 resistive elements --Temperature compensated --End to end resistance, 20% --Terminal voltages, 5V * Low power CMOS --VCC = 5V --Active current, 3mA max. --Standby current, 750A max. * High reliability --Endurance, 100,000 data changes per bit --Register data retention, 100 years * X9C102 = 1k * X9C103 = 10k * X9C503 = 50k * X9C104 = 100k * Packages --8 Ld SOIC and 8 Ld PDIP * Pb-free plus anneal available (RoHS compliant) BLOCK DIAGRAM
U/D INC CS VCC (Supply Voltage) 7-Bit Up/Down Counter
DESCRIPTION The X9Cxxx are Intersil digitally controlled (XDCP) potentiometers. The device consists of a resistor array, wiper switches, a control section, and nonvolatile memory. The wiper position is controlled by a three-wire interface. The potentiometer is implemented by a resistor array composed of 99 resistive elements and a wiper switching network. Between each element and at either end are tap points accessible to the wiper terminal. The position of the wiper element is controlled by the CS, U/D, and INC inputs. The position of the wiper can be stored in nonvolatile memory and then be recalled upon a subsequent power-up operation. The device can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including: - control - parameter adjustments - signal processing
99 98 97
RH/VH
Up/Down (U/D) Increment (INC) Device Select (CS)
VH/RH Control and Memory RW/VW VL/RL VSS (Ground) General
7-Bit Nonvolatile Memory
96 One of OneHundred Decoder 2 1 0
Transfer Gates
Resistor Array
VCC GND
Store and Recall Control Circuitry
RL/VL RW/VW Detailed
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X9C102, X9C103, X9C104, X9C503
PIN CONFIGURATION
DIP/SOIC INC U/D VH/RH VSS 1 2 3 4 X9C102/103/104/503 8 7 6 5 VCC CS VL/RL VW/RW
ORDERING INFORMATION
PART NUMBER X9C102P X9C102PZ (Note) X9C102PI X9C102PIZ (Note) X9C102S*, ** X9C102SZ* (Note) X9C102SI*, ** X9C102SIZ*, ** (Note) X9C103P X9C103PZ (Note) X9C103PI X9C103PIZ (Note) X9C103S*, ** X9C103SZ*, ** X9C103SI*, ** X9C103SIZ*, ** (Note) X9C503P X9C503PZ (Note) X9C503PI X9C503PIZ (Note) X9C503S* X9C503SZ* (Note) X9C503SI*, ** X9C503SIZ*, ** (Note) X9C104P X9C104PI X9C104PIZ (Note) X9C104S*, ** X9C104SZ*, ** (Note) X9C104SI*, ** X9C104SIZ*, ** (Note) (Note) PART MARKING X9C102P X9C102P Z X9C102P I X9C102P ZI X9C102S X9C102S Z X9C102S I X9C102S ZI X9C103P X9C103P Z X9C103P I X9C103P ZI X9C103S X9C103S Z X9C103S I X9C103S ZI X9C503P X9C503P Z X9C503P I X9C503P ZI X9C503S X9C503S Z X9C503S I X9C503S ZI X9C104P X9C104P I X9C104P ZI X9C104S X9C104S Z X9C104S I X9C104S ZI 100 50 10 RTOTAL (k) 1 TEMPERATURE RANGE (C) 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 PACKAGE 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld PDIP 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) PKG. DWG. # MDP0031 MDP0031 MDP0031 MDP0031 MDP0027 MDP0027 MDP0027 MDP0027 MDP0031 MDP0031 MDP0031 MDP0031 MDP0027 MDP0027 MDP0027 MDP0027 MDP0031 MDP0031 MDP0031 MDP0031 MDP0027 MDP0027 MDP0027 MDP0027 MDP0031 MDP0031 MDP0031 MDP0027 MDP0027 MDP0027 MDP0027
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. *Add "T1" suffix for tape and reel. **Add "T2" suffix for tape and reel.
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FN8222.1 December 20, 2006
X9C102, X9C103, X9C104, X9C503
PIN DESCRIPTIONS Pin
1 2 3
Symbol
INC U/D RH/VH
Brief Description
Increment . The INC input is negative-edge triggered. Toggling INC will move the wiper and either increment or decrement the counter in the direction indicated by the logic level on the U/D input.
Up/Down. The U/D input controls the direction of the wiper movement and whether the counter is incremented or decremented.
RH/VH. The high (VH/RH) terminals of the X9C102/103/104/503 are equivalent to the fixed
terminals of a mechanical potentiometer. The minimum voltage is -5V and the maximum is +5V. The terminology of VH/RH and VL/RL references the relative position of the terminal in relation to wiper movement direction selected by the U/D input and not the voltage potential on the terminal.
4 5
VSS
VSS
VW/RW RL/VL
VW/RW. VW/RW is the wiper terminal, and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the control inputs. The wiper terminal series resistance is typically 40. RL/VL. The low (VL/RL) terminals of the X9C102/103/104/503 are equivalent to the fixed terminals of a mechanical potentiometer. The minimum voltage is -5V and the maximum is +5V. The terminology of VH/RH and VL/RL references the relative position of the terminal in relation to wiper movement direction selected by the U/D input and not the voltage potential on the terminal.
CS. The device is selected when the CS input is LOW. The current counter value is stored in nonvolatile memory when CS is returned HIGH while the INC input is also HIGH. After the store operation is complete the X9C102/103/104/503 device will be placed in the low power standby mode until the device is selected once again. VCC
6
7
CS
8
VCC
3
FN8222.1 December 20, 2006
X9C102, X9C103, X9C104, X9C503
ABSOLUTE MAXIMUM RATINGS Temperature under bias .................... -65C to +135C Storage temperature ......................... -65C to +150C Voltage on CS, INC, U/D and VCC with respect to VSS .................................. -1V to +7V Voltage on VH/RH and VL/RL referenced to VSS ................................... -8V to +8V V = |VH/RH - VL/RL| X9C102 ............................................................... 4V X9C103, X9C503, and X9C104 ......................... 10V Lead temperature (soldering, 10 seconds) ...... +300C IW (10 seconds) ................................................. 8.8mA Power rating X9C102 ........................................ 16mW Power rating X9C103/104/503 .......................... 10mW COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS Temperature
Commercial Industrial
Min.
0C -40C
Max.
+70C +85C
Supply Voltage (VCC)
X9C102/103/104/503
Limits
5V 10%
POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Limits Symbol
RTOTAL VVH/RH VVL/RL IW RW
Parameter
End to end resistance variation VH terminal voltage VL terminal voltage Wiper current Wiper resistance Noise (5) Resolution Absolute Relative linearity(1)
Min.
-20 -5 -5 -4.4
Typ.
Max.
+20 +5 +5 4.4
Unit
% V V mA dBV %
Test Conditions/Notes
40 -120 1 -1 -0.2 300(5) 600(5) 20 10/10/25
100
Wiper Current = 1mA Ref. 1kHz VW(n)(actual) - VW(n)(expected) VW(n + 1)(actual) - [VW(n) + MI] X9C103/503/104 X9C102 See Circuit #3, Macro Model
+1 +0.2
MI(3) MI(3) ppm/C ppm/C ppm/C pF
linearity(2)
RTOTAL temperature coefficient RTOTAL temperature coefficient Ratiometric temperature coefficient CH/CL/CW
(5)
Potentiometer capacitances
Notes: (1) (2) (3) (4) (5)
Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = [VW(n)(actual) - VW(n)(expected )] = 1 MI Maximum. Relative linearity is a measure of the error in step size between taps = VW(n + 1) - [VW(n) + MI] = +0.2 MI. 1 MI = Minimum Increment = RTOT/99 Typical values are for TA = +25C and nominal supply voltage. This parameter is not 100% tested.
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FN8222.1 December 20, 2006
X9C102, X9C103, X9C104, X9C503
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Limits Symbol
ICC ISB ILI VIH VIL CIN(5)
Parameter
VCC active current Standby supply current CS, INC, U/D input leakage current CS, INC, U/D input HIGH voltage CS, INC, U/D input LOW voltage CS, INC, U/D input capacitance
Min. Typ.(4)
1 200
Max.
3 750 10
Unit
mA A A V
Test Conditions
CS = VIL, U/D = VIL or VIH and INC = 0.4V to 2.4V @ max. tCYC CS = VCC - 0.3V, U/D and INC = VSS or VCC - 0.3V VIN = VSS to VCC
2 0.8 10
V pF VCC = 5V, VIN = VSS, TA = 25C, f = 1MHz
ENDURANCE AND DATA RETENTION Parameter
Minimum endurance Data retention
Min.
100,000 100
Unit
Data changes per bit per register years
Test Circuit #1
V R /R H VS
Test Circuit #2
VH/RH Test Point Test Point V W /R W V L /R L VW/RW Force Current VL/RL
Test Circuit #3
Macro Model RL CL 10pF RTOTAL CH CW 25pF RW 10pF RH
A.C. CONDITIONS OF TEST
Input pulse levels Input rise and fall times Input reference levels 0V to 3V 10ns 1.5V
5
FN8222.1 December 20, 2006
X9C102, X9C103, X9C104, X9C503
A.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified) Limits Symbol tCl tlD tDI tlL tlH tlC tCPH tCPH tIW (5) tCYC tR, tF(5) tPU(5) tR VCC(5) Parameter CS to INC setup INC HIGH to U/D change U/D to INC setup INC LOW period INC HIGH period INC inactive to CS inactive CS deselect time (STORE) CS deselect time (NO STORE) INC to VW/RW change INC cycle time INC input rise and fall time Power-up to wiper stable VCC power-up rate Min. 100 100 2.9 1 1 1 20 100
2 500 500 0.2 50
Typ.(6)
Max.
100
Unit ns ns s s s s ms ns s s s s V/ms
POWER-UP AND DOWN REQUIREMENTS At all times, voltages on the potentiometer pins must be less than VCC. The recall of the wiper position from nonvolatile memory is not in effect until the VCC supply reaches its final value. The VCC ramp rate spec is always in effect. A.C. TIMING
CS tCYC tCI INC tID U/D tIW VW MI (8) tDI tF tIL tIH tIC tCPH 90% 90% 10% tR
Notes: (6) Typical values are for TA = 25C and nominal supply voltage. (7) This parameter is periodically sampled and not 100% tested. (8) MI in the A.C. timing diagram refers to the minimum incremental change in the VW output due to a change in the wiper position.
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FN8222.1 December 20, 2006
X9C102, X9C103, X9C104, X9C503
DETAILED PIN DESCRIPTIONS RH/VH and RL/VL The high (VH/RH) and low (VL/RL) terminals of the X9C102/103/104/503 are equivalent to the fixed terminals of a mechanical potentiometer. The minimum voltage is -5V and the maximum is +5V. The terminology of VH/RH and VL/RL references the relative position of the terminal in relation to wiper movement direction selected by the U/D input and not the voltage potential on the terminal. RW/VW VW/RW is the wiper terminal, and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the control inputs. The wiper terminal series resistance is typically 40. Up/Down (U/D) The U/D input controls the direction of the wiper movement and whether the counter is incremented or decremented. Increment (INC) The INC input is negative-edge triggered. Toggling INC will move the wiper and either increment or decrement the counter in the direction indicated by the logic level on the U/D input. Chip Select (CS) The device is selected when the CS input is LOW. The current counter value is stored in nonvolatile memory when CS is returned HIGH while the INC input is also HIGH. After the store operation is complete the X9C102/103/104/503 device will be placed in the low power standby mode until the device is selected once again. PIN CONFIGURATION
DIP/SOIC INC U/D VH/RH VSS 1 2 3 4 X9C102/103/104/503 8 7 6 5 VCC CS VL/RL VW/RW
PIN NAMES Symbol
VH /RH VW/RW VL/RL VSS VCC U/D INC CS NC
Description
High Terminal Wiper Terminal Low Terminal Ground Supply Voltage Up/Down Control Input Increment Control Input Chip Select Control Input No Connection
PRINCIPLES OF OPERATION There are three sections of the X9Cxxx: the input control, counter and decode section; the nonvolatile memory; and the resistor array. The input control section operates just like an up/down counter. The output of this counter is decoded to turn on a single electronic switch connecting a point on the resistor array to the wiper output. Under the proper conditions the contents of the counter can be stored in nonvolatile memory and retained for future use. The resistor array is comprised of 99 individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. That is, the counter does not wrap around when clocked to either extreme. The electronic switches on the device operate in a "make before break" mode when the wiper changes tap positions. If the wiper is moved several positions, multiple taps are connected to the wiper for tIW (INC to VW/RW change). The RTOTAL value for the device can temporarily be reduced by a significant amount if the wiper is moved several positions. When the device is powered-down, the last wiper position stored will be maintained in the nonvolatile memory. When power is restored, the contents of the memory are recalled and the wiper is set to the value last stored.
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FN8222.1 December 20, 2006
X9C102, X9C103, X9C104, X9C503
INSTRUCTIONS AND PROGRAMMING The INC, U/D and CS inputs control the movement of the wiper along the resistor array. With CS set LOW the device is selected and enabled to respond to the U/D and INC inputs. HIGH to LOW transitions on INC will increment or decrement (depending on the state of the U/D input) a seven-bit counter. The output of this counter is decoded to select one of one-hundred wiper positions along the resistive array. The value of the counter is stored in nonvolatile memory whenever CS transitions HIGH while the INC input is also HIGH. The system may select the X9Cxxx, move the wiper, and deselect the device without having to store the latest wiper position in nonvolatile memory. After the wiper movement is performed as described above and once the new position is reached, the system must keep INC LOW while taking CS HIGH. The new wiper position will be maintained until changed by the system or until a power-down/up cycle recalled the previously stored data. This procedure allows the system to always power-up to a preset value stored in nonvolatile memory; then during system operation minor adjustments could be made. The adjustments might be based on user preference: system parameter changes due to temperature drift, etc... The state of U/D may be changed while CS remains LOW. This allows the host system to enable the device and then move the wiper up and down until the proper trim is attained. MODE SELECTION CS
L L H H X L L L
INC
U/D
H L X X X H L Wiper Up Wiper Down
Mode
Store Wiper Position Standby Current No Store, Return to Standby Wiper Up (not recommended) Wiper Down (not recommended)
SYMBOL TABLE
WAVEFORM INPUTS Must be steady May change from Low to High May change from High to Low Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from Low to High Will change from High to Low Changing: State Not Known Center Line is High Impedance
8
FN8222.1 December 20, 2006
X9C102, X9C103, X9C104, X9C503
PERFORMANCE CHARACTERISTICS Contact the factory for more information. APPLICATIONS INFORMATION Electronic digitally controlled (XCDP) potentiometers provide three powerful application advantages; (1) the variability and reliability of a solid-state potentiometer, (2) the flexibility of computer-based digital controls, and (3) the retentivity of nonvolatile memory used for the storage of multiple potentiometer settings or data. Basic Configurations of Electronic Potentiometers
VR VH/RH VR
VW/RW
VL/RL I Three terminal potentiometer; variable voltage divider Two terminal variable resistor; variable current
Basic Circuits
Buffered Reference Voltage R1 +V VW + - -5V VOUT = VW/RW (a) (b) +5V VREF OP-07 VOUT +V VW/RW VO = (1+R2/R1)VS VW/RW X Cascading Techniques +V +V Noninverting Amplifier +5V VS + - -5V R2 R1 LM308A VO
Voltage Regulator
Offset Voltage Adjustment R1 R2
Comparator with Hysteresis VS LT311A - +
VIN
317 R1 Iadj R2
VO (REG)
VS 100k - + TL072 10k 10k 10k -12V VO
VO
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
VUL = {R1/(R1 + R2)} VO(max) VLL = {R1/(R1 + R2)} VO(min) (for additional circuits see AN115)
}
R1
}
R2
+12V
9
FN8222.1 December 20, 2006
X9C102, X9C103, X9C104, X9C503 Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL "X"
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L 4 4
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. L 2/01
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FN8222.1 December 20, 2006
X9C102, X9C103, X9C104, X9C503 Plastic Dual-In-Line Packages (PDIP)
D E N PIN #1 INDEX
SEATING PLANE L e b
A2
A c
E1
A1 NOTE 5
eA eB
1
2 b2
N/2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE SYMBOL A A1 A2 b b2 c D E E1 e eA eB L N NOTES: 1. Plastic or metal protrusions of 0.010" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 4. Dimension eB is measured with the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. PDIP8 0.210 0.015 0.130 0.018 0.060 0.010 0.375 0.310 0.250 0.100 0.300 0.345 0.125 8 PDIP14 0.210 0.015 0.130 0.018 0.060 0.010 0.750 0.310 0.250 0.100 0.300 0.345 0.125 14 PDIP16 0.210 0.015 0.130 0.018 0.060 0.010 0.750 0.310 0.250 0.100 0.300 0.345 0.125 16 PDIP18 0.210 0.015 0.130 0.018 0.060 0.010 0.890 0.310 0.250 0.100 0.300 0.345 0.125 18 PDIP20 0.210 0.015 0.130 0.018 0.060 0.010 1.020 0.310 0.250 0.100 0.300 0.345 0.125 20 TOLERANCE MAX MIN 0.005 0.002 +0.010/-0.015 +0.004/-0.002 0.010 +0.015/-0.010 0.005 Basic Basic 0.025 0.010 Reference Rev. B 2/99 2 1 NOTES
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 11
FN8222.1 December 20, 2006

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